DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Jihun | - |
dc.contributor.author | Kim, Joonsung | - |
dc.contributor.author | Park, Pyeongsu | - |
dc.contributor.author | Kim, Jong | - |
dc.contributor.author | Kim, Jangwoo | - |
dc.date.accessioned | 2019-04-07T18:54:03Z | - |
dc.date.available | 2019-04-07T18:54:03Z | - |
dc.date.created | 2018-04-23 | - |
dc.date.issued | 2018-01 | - |
dc.identifier.issn | 1556-6056 | - |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/96090 | - |
dc.description.abstract | Solid-State Drives (SSDs) are widely deployed for high throughput and low latency. However, the unpredictable access latency of SSDs makes it difficult to satisfy quality-of-service requirements and fully achieve the performance potential. In fact, it has been a fundamental challenge to accurately predict the access latency of modern SSDs performing many non-disclosed, device-specific intra-SSD optimizations. In this paper, we propose SSDcheck, a novel SSD performance model which accurately predicts the latency of future SSD accesses. After first identifying write buffer (WB) and garbage collection (GC) as the key components in modeling the access latency, we develop diagnosis snippets to identify the target SSDs critical intra-SSD parameters (e.g., WB size). Finally, we construct the SSDs access-latency model with the identified parameters. Our system-level evaluations using five commodity SSDs show that SSDcheck achieves up to 93 percent prediction accuracy. Our real-world prototype applying an SSDcheck-aware system-level request scheduling can significantly improve both throughput and tail latency by up to 2.1x and 1.46x, respectively. | - |
dc.language | English | - |
dc.publisher | IEEE COMPUTER SOC | - |
dc.relation.isPartOf | IEEE COMPUTER ARCHITECTURE LETTERS | - |
dc.title | SSD Performance Modeling Using Bottleneck Analysis | - |
dc.type | Article | - |
dc.identifier.doi | 10.1109/LCA.2017.2779122 | - |
dc.type.rims | ART | - |
dc.identifier.bibliographicCitation | IEEE COMPUTER ARCHITECTURE LETTERS, v.17, no.1, pp.80 - 83 | - |
dc.identifier.wosid | 000427690300020 | - |
dc.citation.endPage | 83 | - |
dc.citation.number | 1 | - |
dc.citation.startPage | 80 | - |
dc.citation.title | IEEE COMPUTER ARCHITECTURE LETTERS | - |
dc.citation.volume | 17 | - |
dc.contributor.affiliatedAuthor | Kim, Jihun | - |
dc.contributor.affiliatedAuthor | Kim, Jong | - |
dc.identifier.scopusid | 2-s2.0-85037615238 | - |
dc.description.journalClass | 1 | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.type.docType | Article | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
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