A Novel Ternary Multiplier based on Ternary CMOS Compact Model

Abstract

Multiple-valued logic (MVL) has potential advantages for energy-efficient design by reducing a circuit complexity. Because of physical device and circuit realization issues, however, there are relatively small number of researches on MVL circuit designs. We design a novel ternary multiplier based on a ternary CMOS (T-CMOS) compact model. To estimate performance and energy efficiency of our ternary design, we construct a standard ternary-cell library and exploit a ternary static timing analysis (T-STA). The proposed ternary multiplier design achieves significant total power reduction and performance improvement over conventional ternary design.