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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | JINSEOK, KIM | - |
| dc.contributor.author | JONGEUN, KOO | - |
| dc.contributor.author | TAESU, KIM | - |
| dc.contributor.author | YUL, HWA KIM | - |
| dc.contributor.author | HYUNGJUN, KIM | - |
| dc.contributor.author | YOOSEUNGHYUN | - |
| dc.contributor.author | KIM, JAE JOON | - |
| dc.date.accessioned | 2020-04-16T04:53:29Z | - |
| dc.date.available | 2020-04-16T04:53:29Z | - |
| dc.date.created | 2020-04-14 | - |
| dc.date.issued | 2019-06-12 | - |
| dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/103461 | - |
| dc.publisher | IEEE | - |
| dc.relation.isPartOf | Symposium on VLSI Circuits | - |
| dc.relation.isPartOf | Proceedings of Symposium on VLSI Circuits | - |
| dc.title | Area-Efficient and Variation-Tolerant In-Memory BNN Computing using 6T SRAM Array | - |
| dc.type | Conference | - |
| dc.type.rims | CONF | - |
| dc.identifier.bibliographicCitation | Symposium on VLSI Circuits | - |
| dc.citation.conferenceDate | 2019-06-09 | - |
| dc.citation.conferencePlace | JA | - |
| dc.citation.title | Symposium on VLSI Circuits | - |
| dc.contributor.affiliatedAuthor | JINSEOK, KIM | - |
| dc.contributor.affiliatedAuthor | JONGEUN, KOO | - |
| dc.contributor.affiliatedAuthor | TAESU, KIM | - |
| dc.contributor.affiliatedAuthor | YUL, HWA KIM | - |
| dc.contributor.affiliatedAuthor | HYUNGJUN, KIM | - |
| dc.contributor.affiliatedAuthor | YOOSEUNGHYUN | - |
| dc.contributor.affiliatedAuthor | KIM, JAE JOON | - |
| dc.description.journalClass | 1 | - |
| dc.description.journalClass | 1 | - |
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Related Researcher
- 김재준KIM, JAE JOON
- Dept. Convergence IT Engineering