Single RRAM Cell-based In-Memory Accelerator Architecture for Binary Neural Networks
- Title
- Single RRAM Cell-based In-Memory Accelerator Architecture for Binary Neural Networks
- Authors
- Oh, H.; Kim, H.; Kim, J.-J.; YUL, HWA KIM; Park, J.; Kang, N.
- Date Issued
- 2021-06
- Publisher
- Institute of Electrical and Electronics Engineers Inc.
- Abstract
- As Binary Neural Networks (BNNs) started to show promising performance with limited memory and computational cost, various RRAM-based in-memory BNN accelerator designs have been proposed. While a single RRAM cell can represent a binary weight, previous designs had to use two RRAM cells for a weight to enable XNOR operation between a binary weight and a binary activation. In this work, we propose to convert the XNOR-based computation to RRAM-friendly multiplication without any accuracy loss so that we can reduce the required number of RRAM cells by half. As the required number of cells to compute a BNN model is reduced, the energy and area overhead is also reduced. Experimental results show that the proposed in-memory accelerator architecture achieves \sim 1.9 \times area efficiency improvement and \sim 1.8 \times energy efficiency improvement over previous architectures on various image classification benchmarks. ? 2021 IEEE.
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/109469
- Article Type
- Conference
- Citation
- 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2021, 2021-06
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