Comparative Analysis between Verilog and Chisel in RISC-V Core Design and Verification
- Title
- Comparative Analysis between Verilog and Chisel in RISC-V Core Design and Verification
- Authors
- Im, Jaekyung; Kang, Seokhyeong
- Date Issued
- 2021-10-07
- Publisher
- Institute of Electrical and Electronics Engineers Inc.
- Abstract
- Chisel is a hardware design method that uses Scala programming language, and exploits many useful features of Scala like object-oriented programming and functional programming. By comparing two equivalent RISC-V core designs, one implemented using each hand-written Verilog code and one using Chisel, this paper compares manual Verilog coding and Chisel coding. The comparison metrics are source-code density, area of synthesized hardware, and RTL simulation run-Time. As a result, Chisel is proved to be more productive than Verilog.
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/109684
- Article Type
- Conference
- Citation
- 18th International System-on-Chip Design Conference, ISOCC 2021, page. 59 - 60, 2021-10-07
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