DC Field | Value | Language |
---|---|---|
dc.contributor.author | Yun, Sangbu | - |
dc.contributor.author | Kong, Byeong Yong | - |
dc.contributor.author | Lee, Youngjoo | - |
dc.date.accessioned | 2022-03-03T04:20:06Z | - |
dc.date.available | 2022-03-03T04:20:06Z | - |
dc.date.created | 2021-12-30 | - |
dc.date.issued | 2022-03 | - |
dc.identifier.issn | 1549-7747 | - |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/110116 | - |
dc.description.abstract | IEEEA practical min-sum algorithm is associated with tree-based comparison units for the check-node operation, being a major bottleneck in designing low-cost and energy-efficient low-density parity-check (LDPC) decoders. In this paper, we present a cost-effective LDPC decoder architecture by changing its internal computing resolution for the power-hungry check-node processing. The proposed mixed-resolution comparison offers significant advantages in terms of both area and energy, while achieving error-correcting performance within 0.3 dB of the previous normalized min-sum (NMS) algorithm for a (1644, 1408) quasi-cyclic LDPC code of the 5G New Radio specifications. Compared to the baseline NMS architecture, the proposed decoder in a 65-nm CMOS technology reduces the hardware complexity and the power consumption by 28.4% and 23.1%, respectively, enhancing the area efficiency by more than 88.2%. | - |
dc.language | English | - |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
dc.relation.isPartOf | IEEE Transactions on Circuits and Systems II: Express Briefs | - |
dc.title | Area-and Energy-Efficient LDPC Decoder Using Mixed-Resolution Check-Node Processing | - |
dc.type | Article | - |
dc.identifier.doi | 10.1109/TCSII.2021.3110953 | - |
dc.type.rims | ART | - |
dc.identifier.bibliographicCitation | IEEE Transactions on Circuits and Systems II: Express Briefs, v.69, no.3, pp.999 - 1003 | - |
dc.identifier.wosid | 000770045800070 | - |
dc.citation.endPage | 1003 | - |
dc.citation.number | 3 | - |
dc.citation.startPage | 999 | - |
dc.citation.title | IEEE Transactions on Circuits and Systems II: Express Briefs | - |
dc.citation.volume | 69 | - |
dc.contributor.affiliatedAuthor | Yun, Sangbu | - |
dc.contributor.affiliatedAuthor | Lee, Youngjoo | - |
dc.identifier.scopusid | 2-s2.0-85114751743 | - |
dc.description.journalClass | 1 | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.type.docType | Article | - |
dc.subject.keywordPlus | DESIGN | - |
dc.subject.keywordPlus | IMPLEMENTATION | - |
dc.subject.keywordPlus | ARCHITECTURE | - |
dc.subject.keywordPlus | ALGORITHM | - |
dc.subject.keywordAuthor | Complexity theory | - |
dc.subject.keywordAuthor | Computer architecture | - |
dc.subject.keywordAuthor | Cost-effective | - |
dc.subject.keywordAuthor | Decoding | - |
dc.subject.keywordAuthor | Energy-efficient | - |
dc.subject.keywordAuthor | Error-correction code | - |
dc.subject.keywordAuthor | Hardware | - |
dc.subject.keywordAuthor | Indexes | - |
dc.subject.keywordAuthor | Iterative decoding | - |
dc.subject.keywordAuthor | LDPC decoding | - |
dc.subject.keywordAuthor | Multiplexing | - |
dc.subject.keywordAuthor | Wireless communication. | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
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