Area-and Energy-Efficient LDPC Decoder Using Mixed-Resolution Check-Node Processing
SCIE
SCOPUS
- Title
- Area-and Energy-Efficient LDPC Decoder Using Mixed-Resolution Check-Node Processing
- Authors
- Yun, Sangbu; Kong, Byeong Yong; Lee, Youngjoo
- Date Issued
- 2022-03
- Publisher
- Institute of Electrical and Electronics Engineers Inc.
- Abstract
- IEEEA practical min-sum algorithm is associated with tree-based comparison units for the check-node operation, being a major bottleneck in designing low-cost and energy-efficient low-density parity-check (LDPC) decoders. In this paper, we present a cost-effective LDPC decoder architecture by changing its internal computing resolution for the power-hungry check-node processing. The proposed mixed-resolution comparison offers significant advantages in terms of both area and energy, while achieving error-correcting performance within 0.3 dB of the previous normalized min-sum (NMS) algorithm for a (1644, 1408) quasi-cyclic LDPC code of the 5G New Radio specifications. Compared to the baseline NMS architecture, the proposed decoder in a 65-nm CMOS technology reduces the hardware complexity and the power consumption by 28.4% and 23.1%, respectively, enhancing the area efficiency by more than 88.2%.
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/110116
- DOI
- 10.1109/TCSII.2021.3110953
- ISSN
- 1549-7747
- Article Type
- Article
- Citation
- IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 3, page. 999 - 1003, 2022-03
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