DC Field | Value | Language |
---|---|---|
dc.contributor.author | Park, Naebeom | - |
dc.contributor.author | Ryu, Sungju | - |
dc.contributor.author | Kung, Jaeha | - |
dc.contributor.author | Kim, Jae-Joon | - |
dc.date.accessioned | 2022-03-16T02:50:02Z | - |
dc.date.available | 2022-03-16T02:50:02Z | - |
dc.date.created | 2022-03-11 | - |
dc.date.issued | 2021-11 | - |
dc.identifier.issn | 1084-4309 | - |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/110870 | - |
dc.description.abstract | This article discusses the high-performance near-memory neural network (NN) accelerator architecture utilizing the logic die in three-dimensional (3D) High Bandwidth Memory- (HBM) like memory. As most of the previously reported 3D memory-based near-memory NN accelerator designs used the Hybrid Memory Cube (HMC) memory, we first focus on identifying the key differences between HBM and HMC in terms of near-memory NN accelerator design. One of the major differences between the two 3D memories is that HBM has the centralized through-silicon-via (TSV) channels while HMC has distributed TSV channels for separate vaults. Based on the observation, we introduce the Round-Robin Data Fetching and Groupwise Broadcast schemes to exploit the centralized TSV channels for improvement of the data feeding rate for the processing elements. Using synthesized designs in a 28-nm CMOS technology, performance and energy consumption of the proposed architectures with various dataflow models are evaluated. Experimental results show that the proposed schemes reduce the runtime by 16.4-39.3% on average and the energy consumption by 2.1-5.1% on average compared to conventional data fetching schemes. | - |
dc.language | English | - |
dc.publisher | Association for Computing Machinary, Inc. | - |
dc.relation.isPartOf | ACM Transactions on Design Automation of Electronic Systems | - |
dc.title | High-throughput Near-Memory Processing on CNNs with 3D HBM-like Memory | - |
dc.type | Article | - |
dc.identifier.doi | 10.1145/3460971 | - |
dc.type.rims | ART | - |
dc.identifier.bibliographicCitation | ACM Transactions on Design Automation of Electronic Systems, v.26, no.6 | - |
dc.identifier.wosid | 000756208000008 | - |
dc.citation.number | 6 | - |
dc.citation.title | ACM Transactions on Design Automation of Electronic Systems | - |
dc.citation.volume | 26 | - |
dc.contributor.affiliatedAuthor | Park, Naebeom | - |
dc.contributor.affiliatedAuthor | Ryu, Sungju | - |
dc.contributor.affiliatedAuthor | Kim, Jae-Joon | - |
dc.identifier.scopusid | 2-s2.0-85116630258 | - |
dc.description.journalClass | 1 | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.type.docType | Article | - |
dc.subject.keywordPlus | DEEP NEURAL-NETWORKS | - |
dc.subject.keywordAuthor | Neural network accelerator | - |
dc.subject.keywordAuthor | HBM | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Software Engineering | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
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