DC Field | Value | Language |
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dc.contributor.author | Baek, RH | - |
dc.contributor.author | BAEK, CHANG KI | - |
dc.contributor.author | Lee, SH | - |
dc.contributor.author | Suk, SD | - |
dc.contributor.author | Li, M | - |
dc.contributor.author | Yeoh, YY | - |
dc.contributor.author | Yeo, KH | - |
dc.contributor.author | Kim, DW | - |
dc.contributor.author | LEE, JEONG SOO | - |
dc.contributor.author | Kim, DM | - |
dc.contributor.author | JEONG, YOON HA | - |
dc.date.accessioned | 2016-03-31T08:11:05Z | - |
dc.date.available | 2016-03-31T08:11:05Z | - |
dc.date.created | 2011-03-18 | - |
dc.date.issued | 2011-02 | - |
dc.identifier.issn | 0741-3106 | - |
dc.identifier.other | 2011-OAK-0000029376 | - |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/14746 | - |
dc.description.abstract | Presented in this letter are the C-V data, measured from nanowire capacitors, which have been fabricated by connecting in parallel a large number of identically processed nanowire FETs. The C-V curves were examined over a range from accumulation to inversion with varying frequencies and at different electrode configurations. The gate response of the undoped and floating channel is investigated using C-V data, and the inversion charge and carrier mobility are accurately extracted by eliminating the effects of parasitic capacitances and series resistance R(sd). These observed data are compared with the data from planar MOS capacitor. | - |
dc.description.statementofresponsibility | X | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELELCTRONICS ENGINEERS INC. | - |
dc.relation.isPartOf | IEEE Electron Device Letters | - |
dc.title | C-V Characteristics in Undoped Gate-All-Around Nanowire FET Array | - |
dc.type | Article | - |
dc.contributor.college | 창의IT융합공학과 | - |
dc.identifier.doi | 10.1109/LED.2010.2092409 | - |
dc.author.google | Baek, RH | - |
dc.author.google | Baek, CK | - |
dc.author.google | Lee, SH | - |
dc.author.google | Suk, SD | - |
dc.author.google | Li, M | - |
dc.author.google | Yeoh, YY | - |
dc.author.google | Yeo, KH | - |
dc.author.google | Kim, DW | - |
dc.author.google | Lee, JS | - |
dc.author.google | Kim, DM | - |
dc.author.google | Jeong, YH | - |
dc.relation.volume | 32 | - |
dc.relation.issue | 2 | - |
dc.relation.startpage | 116 | - |
dc.relation.lastpage | 118 | - |
dc.contributor.id | 10644344 | - |
dc.relation.journal | IEEE ELECTRON DEVICE LETTERS | - |
dc.relation.index | SCI급, SCOPUS 등재논문 | - |
dc.relation.sci | SCI | - |
dc.collections.name | Journal Papers | - |
dc.type.rims | ART | - |
dc.identifier.bibliographicCitation | IEEE Electron Device Letters, v.32, no.2, pp.116 - 118 | - |
dc.identifier.wosid | 000286677700002 | - |
dc.date.tcdate | 2019-01-01 | - |
dc.citation.endPage | 118 | - |
dc.citation.number | 2 | - |
dc.citation.startPage | 116 | - |
dc.citation.title | IEEE Electron Device Letters | - |
dc.citation.volume | 32 | - |
dc.contributor.affiliatedAuthor | Baek, RH | - |
dc.contributor.affiliatedAuthor | BAEK, CHANG KI | - |
dc.contributor.affiliatedAuthor | LEE, JEONG SOO | - |
dc.contributor.affiliatedAuthor | JEONG, YOON HA | - |
dc.identifier.scopusid | 2-s2.0-79151476001 | - |
dc.description.journalClass | 1 | - |
dc.description.journalClass | 1 | - |
dc.description.wostc | 7 | - |
dc.type.docType | Article | - |
dc.subject.keywordAuthor | C-V curves | - |
dc.subject.keywordAuthor | gate-all-around (GAA) | - |
dc.subject.keywordAuthor | mobility | - |
dc.subject.keywordAuthor | nanowire | - |
dc.subject.keywordAuthor | twin silicon nanowire field effect transistor (TSNWFET) | - |
dc.subject.keywordAuthor | undoped floating channel | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
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