DC Field | Value | Language |
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dc.contributor.author | Jae Hoon Kim | - |
dc.contributor.author | Kim, YH | - |
dc.date.accessioned | 2016-03-31T08:24:05Z | - |
dc.date.available | 2016-03-31T08:24:05Z | - |
dc.date.created | 2013-12-17 | - |
dc.date.issued | 2013-09 | - |
dc.identifier.issn | 0026-2692 | - |
dc.identifier.other | 2013-OAK-0000028412 | - |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/15221 | - |
dc.description.abstract | This paper presents an efficient approach to statistical leakage analysis (SLA) that can estimate the arbitrary n-sigma leakage currents of the VLSI system for the probability density function (PDF) of a lognormal distribution. Unlike existing SLA approaches, the proposed method uses deterministic cell leakage models and gate-level deterministic leakage analysis, and thus, provides significantly reduced analysis complexity. Providing the n-sigma chip leakage current for the PDF of WM-based SLA with a computational complexity of O(N), where N is the number of cells in a chip, the proposed approach is a promising candidate for the analysis of recent technology (comprising billions of logic cells in a chip) to address the high-complexity of conventional approaches to SLA. Compared to conventional WM-based SLA, when the value of n was 5.1803, 3.6022, and 2.8191, the average absolute errors of n-sigma chip leakage current exhibited by the proposed approach were 5.08%, 4.73%, and 4.45%, respectively. (C) 2013 Elsevier Ltd. All rights reserved. | - |
dc.description.statementofresponsibility | X | - |
dc.language | English | - |
dc.publisher | ELSEVIER | - |
dc.relation.isPartOf | Microelectronics Journal | - |
dc.subject | Wilkinson&apos | - |
dc.subject | s method | - |
dc.subject | Computational complexity | - |
dc.subject | Gate-level deterministic leakage analysis | - |
dc.subject | PARAMETRIC YIELD ESTIMATION | - |
dc.subject | VARIABILITY | - |
dc.subject | POWER | - |
dc.title | Efficient statistical leakage analysis using deterministic cell leakage models | - |
dc.type | Article | - |
dc.contributor.college | 전자전기공학과 | - |
dc.identifier.doi | 10.1016/J.MEJO.2013.06.014 | - |
dc.author.google | Kim, JH | - |
dc.author.google | Kim, YH | - |
dc.relation.volume | 44 | - |
dc.relation.issue | 9 | - |
dc.relation.startpage | 764 | - |
dc.relation.lastpage | 773 | - |
dc.contributor.id | 10176127 | - |
dc.relation.journal | Microelectronics Journal | - |
dc.relation.index | SCI급, SCOPUS 등재논문 | - |
dc.relation.sci | SCIE | - |
dc.collections.name | Journal Papers | - |
dc.type.rims | ART | - |
dc.identifier.bibliographicCitation | Microelectronics Journal, v.44, no.9, pp.764 - 773 | - |
dc.identifier.wosid | 000325906800005 | - |
dc.date.tcdate | 2018-03-23 | - |
dc.citation.endPage | 773 | - |
dc.citation.number | 9 | - |
dc.citation.startPage | 764 | - |
dc.citation.title | Microelectronics Journal | - |
dc.citation.volume | 44 | - |
dc.contributor.affiliatedAuthor | Kim, YH | - |
dc.identifier.scopusid | 2-s2.0-84884499117 | - |
dc.description.journalClass | 1 | - |
dc.description.journalClass | 1 | - |
dc.description.scptc | 0 | * |
dc.date.scptcdate | 2018-05-121 | * |
dc.type.docType | Article | - |
dc.subject.keywordAuthor | Wilkinson&apos | - |
dc.subject.keywordAuthor | s method | - |
dc.subject.keywordAuthor | Computational complexity | - |
dc.subject.keywordAuthor | Gate-level deterministic leakage analysis | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalWebOfScienceCategory | Nanoscience & Nanotechnology | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Science & Technology - Other Topics | - |
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