DC Field | Value | Language |
---|---|---|
dc.contributor.author | Mukhopadhyay, S | - |
dc.contributor.author | Rao, RM | - |
dc.contributor.author | Kim, JJ | - |
dc.contributor.author | Chuang, CT | - |
dc.date.accessioned | 2017-07-19T12:27:40Z | - |
dc.date.available | 2017-07-19T12:27:40Z | - |
dc.date.created | 2016-02-28 | - |
dc.date.issued | 2016-02 | - |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/35850 | - |
dc.description.abstract | One of the most aggressive uses of dynamic voltage scaling is timing speculation, which in turn requires fast correction of timing errors. The fastest existing error correction technique imposes a one-cycle time penalty only, but it is restricted to two-phase transparent latch-based pipelines. We perform one-cycle error correction by gating only the main latch in each stage of the pipeline that precedes a failed stage. This new method is applicable to widely used clocking elements, such as flip-flops and pulsed latches. Because it prevents inputs arriving at a stage, which is stalled, it can also be used in pipelines with multiple fan-in, fan-out, and looping. Simulations show an energy saving of 8%-12% with a target throughput of 0.9 instructions per cycle, and 15%-18% when the target is 0.8. © 1993-2012 IEEE. | - |
dc.language | English | - |
dc.publisher | IEEE | - |
dc.relation.isPartOf | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.title | One-cycle correction of timing errors in pipelines with standard clocked elements | - |
dc.type | Article | - |
dc.identifier.doi | 10.1109/TVLSI.2015.2409118 | - |
dc.type.rims | ART | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.24, no.2, pp.600 - 612 | - |
dc.identifier.wosid | 000369479500017 | - |
dc.date.tcdate | 2019-03-01 | - |
dc.citation.endPage | 612 | - |
dc.citation.number | 2 | - |
dc.citation.startPage | 600 | - |
dc.citation.title | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.citation.volume | 24 | - |
dc.contributor.affiliatedAuthor | Kim, JJ | - |
dc.identifier.scopusid | 2-s2.0-84925872430 | - |
dc.description.journalClass | 1 | - |
dc.description.journalClass | 1 | - |
dc.description.wostc | 3 | - |
dc.description.scptc | 38 | * |
dc.date.scptcdate | 2018-05-121 | * |
dc.description.isOpenAccess | N | - |
dc.type.docType | Article | - |
dc.subject.keywordPlus | DYNAMIC VOLTAGE | - |
dc.subject.keywordPlus | POWER | - |
dc.subject.keywordPlus | SYSTEM | - |
dc.subject.keywordAuthor | Error correction | - |
dc.subject.keywordAuthor | low-voltage operation | - |
dc.subject.keywordAuthor | timing speculation | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
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