A low-voltage OP amp with digitally controlled algorithmic approximation
SCIE
SCOPUS
- Title
- A low-voltage OP amp with digitally controlled algorithmic approximation
- Authors
- Jee, D.-W; Park, S.-J; Park, H.-J; Sim, J.-Y.
- Date Issued
- 2008-01
- Publisher
- .
- Abstract
- This paper presents a new architecture of digitally controlled algorithmic OP amp suitable for scaled CMOS technologies. With inverter-based gain stages and digitally-assisted damping control, the amplifier achieves high-gain and wide input/output ranges even at the minimally allowable supply voltage by digital circuits. The amplifier, implemented in a standard 0.18 mu m CMOS, shows a DC gain of 73 dB and 95 % settling time of 41 ns at 0.5 V step input.
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/35872
- DOI
- 10.1109/CICC.2008.4672131
- ISSN
- 0886-5930
- Article Type
- Article
- Citation
- Proceedings of the Custom Integrated Circuits Conference, page. 499 - 502, 2008-01
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- There are no files associated with this item.
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