Energy-scalable 4KB LDPC decoding architecture for NAND-flash-based storage systems
SCIE
SCOPUS
- Title
- Energy-scalable 4KB LDPC decoding architecture for NAND-flash-based storage systems
- Authors
- Lee, Y; Jung, J; Park, IC
- Date Issued
- 2016-02
- Publisher
- IEICE
- Abstract
- This paper presents a novel low-power decoder architecture for the (36420, 32778) binary LDPC code targeting energy-efficient NAND-flash-based mobile devices. The proposed energy-scalable decoding algorithm reduces the operating bit-width of decoding function units at the early-use stage where the channel condition is good enough to lower the precision of computation. Based on a flexible adder structure, the decoding energy of the proposed LDPC decoder can be reduced by freezing the unnecessary parts of hardware resources. A prototype 4KB LDPC decoder is designed in a 65nm CMOS technology, which achieves an average decoding throughput of 8.13Gb/s with 1.2M equivalent gates. The power consumption of the decoder ranges from 397mW to 563mW depending on operating conditions.
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/37528
- DOI
- 10.1587/TRANSELE.E99.C.293
- ISSN
- 1745-1353
- Article Type
- Article
- Citation
- IEICE TRANSACTIONS ON ELECTRONICS, vol. E99C, no. 2, page. 291 - 301, 2016-02
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