Area and energy efficient 802.11ad LDPC decoding processor
SCIE
SCOPUS
- Title
- Area and energy efficient 802.11ad LDPC decoding processor
- Authors
- Li, M; Lee, Y; Huang, YX; Van der Perre, L
- Date Issued
- 2015-02-19
- Publisher
- IEE
- Abstract
- The design of multi-Gbit/s low-density parity-check code (LDPC) decoders has become a hot topic in recent years to meet the growing demand of the transformation towards 4G. An area and energy efficient multi-Gbit/s LDPC decoder engine with a fully paralleled layered architecture based on an application-specific instruction set processor (ASIP) using Synopsys IP designer is presented. When the ASIP core is instantiated for 802.11ad, it achieved a throughput of up to 7 Gbit/s at three iterations with a latency of 95 ns, a record energy efficiency of 2.5 pJ/bit/iteration and an area efficiency of 54.5 Gbit/s/sq-m in CMOS 28 nm technology for the 1/2 rate, showing it to be competitive against published ASIC solutions.
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/37536
- DOI
- 10.1049/EL.2014.4263
- ISSN
- 0013-5194
- Article Type
- Article
- Citation
- ELECTRONICS LETTERS, vol. 51, no. 4, page. 339 - 340, 2015-02-19
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- There are no files associated with this item.
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