Single-step glitch-free NAND-based digitally controlled delay lines using dual loops
SCIE
SCOPUS
- Title
- Single-step glitch-free NAND-based digitally controlled delay lines using dual loops
- Authors
- Lee, Y; Park, IC
- Date Issued
- 2014-06-19
- Publisher
- IEE
- Abstract
- To remove glitches occurring in NAND-based digitally controlled delay lines (DCDLs), a novel glitch-free architecture is presented. Compared with the previous structures requiring multiple control steps, the proposed DCDL employs a self-delayed inner loop to remove all the glitches by applying a single-step control-code switching, reducing the control complexity remarkably without increasing the minimum delay as well as the resolution.
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/37543
- DOI
- 10.1049/EL.2014.0331
- ISSN
- 0013-5194
- Article Type
- Article
- Citation
- ELECTRONICS LETTERS, vol. 50, no. 13, page. 930 - 931, 2014-06-19
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- There are no files associated with this item.
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