Junction Design Strategy for Si Bulk FinFETs for System-on-Chip Applications Down to the 7-nm Node
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SCOPUS
- Title
- Junction Design Strategy for Si Bulk FinFETs for System-on-Chip Applications Down to the 7-nm Node
- Authors
- Yoon, JS; Jeong, EY; Baek, CK; Kim, YR; Hong, JH; Lee, JS; Baek, RH; Jeong, YH
- Date Issued
- 2015-10
- Publisher
- IEEE
- Abstract
- DC/AC characteristics of Si bulk FinFETs including middle-of-line levels are precisely investigated using well-calibrated 3-D device simulations for system-on-chip applications. Scaling the fin widths down to 5 nm effectively enhances gate-to-channel controllability and improves RC delay, but a dramatic increase in band-to-band tunneling currents from source-to-drain does not satisfy low-power application in the 7-nm node. All lightly-doped extension regions as a solution could improve band-to-band tunneling currents and total gate capacitances because of better short-channel immunity and lower parasitic capacitances, respectively. Using systematic TCAD-based RC calculation, we suggest optimized overlap/underlap lengths in the 7-nm node FinFETs to overcome the scaling limitations.
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/37757
- DOI
- 10.1109/LED.2015.2464706
- ISSN
- 0741-3106
- Article Type
- Article
- Citation
- IEEE ELECTRON DEVICE LETTERS, vol. 36, no. 10, page. 994 - 996, 2015-10
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