DC Field | Value | Language |
---|---|---|
dc.contributor.author | Jeong, EY | - |
dc.contributor.author | Yoon, JS | - |
dc.contributor.author | Baek, CK | - |
dc.contributor.author | Kim, YR | - |
dc.contributor.author | Hong, JH | - |
dc.contributor.author | Lee, JS | - |
dc.contributor.author | Baek, RH | - |
dc.contributor.author | Jeong, YH | - |
dc.date.accessioned | 2017-07-19T13:51:56Z | - |
dc.date.available | 2017-07-19T13:51:56Z | - |
dc.date.created | 2017-02-22 | - |
dc.date.issued | 2015-10 | - |
dc.identifier.issn | 0018-9383 | - |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/37758 | - |
dc.description.abstract | In this brief, we systematically investigated the effects of fin pitch (FP) and fin height (H-fin) on parasitic resistances and capacitances to achieve the best RC delay, which is an adequate metric of the ac behavior of FinFETs, for Si bulk n/pFinFETs in system-on-a-chip applications. The RC delays were directly extracted from the fully calibrated technology computer aided design I-V/C-V simulation results and quantitatively analyzed using parasitic capacitance components, including a middle-of-the line configuration up to Metal 1. When FP increased, the RC delay likewise increased due to greater C-gg. On the other hand, the RC delay mostly decreased due to greater ON-current as the H-fin increased. The RC delay with different power supply voltages (V-DD = 0.55 and 0.75 V) was also studied to see the effect of V-DD scaling. Finally, a selective deposition was suggested to improve the RC delay about 13%. | - |
dc.language | English | - |
dc.publisher | IEEE | - |
dc.relation.isPartOf | IEEE TRANSACTIONS ON ELECTRON DEVICES | - |
dc.title | Investigation of RC Parasitics Considering Middle-of-the-Line in Si-Bulk FinFETs for Sub-14-nm Node Logic Applications | - |
dc.type | Article | - |
dc.identifier.doi | 10.1109/TED.2015.2462760 | - |
dc.type.rims | ART | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON ELECTRON DEVICES, v.62, no.10, pp.3441 - 3444 | - |
dc.identifier.wosid | 000361684000048 | - |
dc.date.tcdate | 2019-02-01 | - |
dc.citation.endPage | 3444 | - |
dc.citation.number | 10 | - |
dc.citation.startPage | 3441 | - |
dc.citation.title | IEEE TRANSACTIONS ON ELECTRON DEVICES | - |
dc.citation.volume | 62 | - |
dc.contributor.affiliatedAuthor | Baek, CK | - |
dc.contributor.affiliatedAuthor | Lee, JS | - |
dc.contributor.affiliatedAuthor | Baek, RH | - |
dc.contributor.affiliatedAuthor | Jeong, YH | - |
dc.identifier.scopusid | 2-s2.0-84958212366 | - |
dc.description.journalClass | 1 | - |
dc.description.journalClass | 1 | - |
dc.description.wostc | 7 | - |
dc.description.scptc | 5 | * |
dc.date.scptcdate | 2018-05-121 | * |
dc.type.docType | Article | - |
dc.subject.keywordAuthor | Bulk | - |
dc.subject.keywordAuthor | fin height (H-fin) | - |
dc.subject.keywordAuthor | fin pitch (FP) | - |
dc.subject.keywordAuthor | FinFET | - |
dc.subject.keywordAuthor | middle-of-the line (MOL) | - |
dc.subject.keywordAuthor | parasitic capacitance | - |
dc.subject.keywordAuthor | RC delay | - |
dc.subject.keywordAuthor | selective deposition | - |
dc.subject.keywordAuthor | system-on-a-Chip (SoC) | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Physics | - |
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