DC Field | Value | Language |
---|---|---|
dc.contributor.author | SUNGJU, RYU | - |
dc.contributor.author | JONGEUN, KOO | - |
dc.contributor.author | KIM, JAE JOON | - |
dc.date.accessioned | 2018-05-10T09:26:05Z | - |
dc.date.available | 2018-05-10T09:26:05Z | - |
dc.date.created | 2018-02-21 | - |
dc.date.issued | 2017-07-24 | - |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/42040 | - |
dc.description.abstract | The elastic clock scheme is a robust design methodology to ensure timing closure under PVT variation using locally generated clocks and handshaking protocol. However, it still has a chance of timing errors due to delay mismatch between the data-path and delay replica. In this paper, we propose a low design overhead timing error correction scheme tailored to elastic clock. In the proposed scheme, a timing error can be corrected within a cycle using clock stretching. The proposed scheme shows 40.3× and 4.6× reduction in timing margin with 9.1% and 9.0% area overhead over the synchronous baseline and elastic clock design, respectively. | - |
dc.publisher | IEEE/ACM | - |
dc.relation.isPartOf | International Symposium on Low Power Electronics and Design (ISLPED) | - |
dc.relation.isPartOf | Proceedings of ISLPED | - |
dc.title | Low Design Overhead Timing Error Correction Scheme for Elastic Clock Methodology | - |
dc.type | Conference | - |
dc.type.rims | CONF | - |
dc.identifier.bibliographicCitation | International Symposium on Low Power Electronics and Design (ISLPED) | - |
dc.citation.conferenceDate | 2017-07-24 | - |
dc.citation.conferencePlace | CH | - |
dc.citation.title | International Symposium on Low Power Electronics and Design (ISLPED) | - |
dc.contributor.affiliatedAuthor | SUNGJU, RYU | - |
dc.contributor.affiliatedAuthor | JONGEUN, KOO | - |
dc.contributor.affiliatedAuthor | KIM, JAE JOON | - |
dc.description.journalClass | 1 | - |
dc.description.journalClass | 1 | - |
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