Area-Efficient One-Cycle Correction Scheme for Timing Errors in Flip-Flop Based Pipelines
- Title
- Area-Efficient One-Cycle Correction Scheme for Timing Errors in Flip-Flop Based Pipelines
- Authors
- JONGEUN, KOO; Song, Eunwoo; Eunhyeok Park; Dongyoung Kim; PARK, JUN KI; SUNGJU, RYU; Sungjoo, Yoo; KIM, JAE JOON
- Date Issued
- 2016-11-09
- Publisher
- IEEE
- Abstract
- We propose a new timing error correction scheme for area-efficient design of flip-flop based pipeline. Key features in the proposed scheme are 1) one-cycle error correction using a new local stalling scheme and 2) selective replacement of the error detection and correction flip-flops in critical paths only. A 32-bit MIPS testchip in a 65 nm CMOS technology has been implemented as a testbed. By employing the proposed scheme in the flop-flop based pipeline, the area overhead due to the retiming process (~21%) in the previous two-phase transparent latch based scheme can be eliminated. In addition, substantial area saving (16%) can be achieved compared to the state-of-the-art flip-flop based scheme thanks to the selective replacement of the error detection and correction flip-flops.
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/42455
- Article Type
- Conference
- Citation
- IEEE Asian Solid-State Circuits Conference (ASSCC), 2016-11-09
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- There are no files associated with this item.
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