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Current Source Model of Combinational Logic Gates for Accurate Gate-level Circuit Analysis and Timing Analysis
- Title
- Current Source Model of Combinational Logic Gates for Accurate Gate-level Circuit Analysis and Timing Analysis
- Date Issued
- 2015-04-28
- Publisher
- IEEE Circuits and Systems Society
- Article Type
- Conference
- Citation
- VLSI Design, Automation and Test (VLSI-DAT 2015), 2015-04-28
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Related Researcher
- 김영환KIM, YOUNG HWAN
- Dept of Electrical Enginrg