Edge Profile Effect of Tunnel Oxide on Erase Threshold Voltage Distributions in Flash Memory Cells

Abstract

The erase threshold-voltage (V-T) distribution in Flash electrically erasable programmable read-only memory cells was investigated versus the tunnel oxide edge profiles in self-aligned shallow trench isolation (SA-STI) and self-aligned poly (SAP) cells. The capacitive coupling with offset voltage correction is transcribed into V-T transient for simulating erase V-T dispersion without numerous full structure device simulations. It is shown that SAP gives rise to smaller V-T dispersion, compared with SA-STI. The V-T dispersion resulting from variations in dielectric thickness and oxide edge profiles is shown to fall far short of observed V-T distribution, calling for examination of additional process and cell parameters.